1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the invention relates to an output noise processing circuit in the semiconductor integrated circuit utilized in, for instance, a dynamic type semiconductor memory (DRAM).
2. Description of the Related Art
In a conventional DRAM of a multibit structure, as shown in FIG. 10, in a fast page mode as one kind of reading operation, output data Dout is output corresponding to the active period of a /CAS (/Column Address Strobe) signal and during other periods an output is placed in a high impedance state (HiZ). Output data Dout in the fast page mode changes between a high level "H" and a high impedance or between a low level "L" and a high impedance.
In a hyper page mode as another kind of reading operation (Extended Data Output mode: EDO mode), as shown in FIG. 10, output data Dout is switched in synchronization with the leading edge of a /CAS signal. This mode is advantageous, since a cycle time can be made short by an amount equivalent to widening of an output window width.
However, since Dout in the hyper page mode changes between a high level "H" and a low level "L", output noises (fluctuations in power source potential or ground potential) are large following a change in output data, especially in the DRAM of a multibit structure. As a result, it is easy for an internal circuit (especially an input circuit) to malfunction due to output noises.
As described above, for the conventional DRAM of a multibit structure, the problem has been that output noises are large in the hyper page mode and thus it is easy for the internal circuit to malfunction due to output noises.